1. Field of the Invention
This invention relates to an insulated gate FET and a method for manufacturing the same, and more particularly to the improvement of a withstanding voltage and latch-up characteristic.
2. Description of the Related Art
At present, semiconductor devices have a problem that a parasitic bipolar transistor will be rendered conductive, that is, a so-called latch-up phenomenon may occur.
In order to prevent occurrence of the latch-up phenomenon, there is provided a method of lowering the performance of the parasitic bipolar transistor by separating the elements from each other by a sufficiently long distance to increase the base length of the parasitic bipolar transistor, for example.
However, recently, the distance between the elements is gradually reduced with an increase in the integration density of the semiconductor device. When the distance between the elements is gradually reduced, the base length of the parasitic bipolar transistor is reduced, thereby permitting the parasitic bipolar transistor to be easily turned on.
In order to solve the above problem, there is provided a method of lowering the performance of the parasitic bipolar transistor by increasing the impurity concentration of the well region to enhance the base impurity concentration of the parasitic bipolar transistor.
Further, the element itself has been miniaturized, and a problem of short channel effect and the like tends to occur. In order to prevent the short channel effect, there is provided a method of lowering the intensity of the electric field near the gate electrode by lowering the drain impurity concentration near the gate electrode, for example. As the above method, several methods using an LDD (Lightly Doped Drain) structure, GDD (Graded Diffused Drain) structure, DDD (Double Diffused Drain) structure and the like are known.
Generally, active elements constituting an IC are operated on a voltage of approx. 5 V, but some elements are operated on a higher voltage of 10 V or more (this type of element is hereinafter referred to as a high voltage element in this specification).
Since a high voltage is applied to the gate, drain and source in the high voltage element, the short channel effect which tends to occur in the miniaturized element may be caused even if the gate length is sufficiently large, for example. In order to solve the above problem, The above-described LDD structure, GDD structure and DDD structure are incorporated into the high voltage element.
Thus, the high voltage element has been miniaturized. Therefore, recently, a latch-up phenomenon has become significant as a problem. However, in the high voltage element, the withstanding voltage of the element will be lowered if the impurity concentration of the well region is enhanced to improve the latch-up resistant property.